1. Field of the Invention
This invention relates generally to a method of manufacturing a nonvolatile semiconductor memory device, and more particularly to a method of manufacturing an erasable programmable nonvolatile semiconductor memory device having two or more gate electrode layers and an offset region.
2. Description of the Related Art
FIG. 1 is a cross-sectional view showing a memory cell portion of a conventional EPROM (erasable programmable read-only memory), for example an EPROM cell having two gate electrode layers and an offset region for increasing a punch-through voltage. An insulating film 12 is formed on a p-type silicon substrate. A floating gate 13 is formed on the insulating film 12. A control gate 15 is formed on an insulating film 14-1 covering the floating gate 13 and an insulating film 14-2 covering the substrate 11. A source region 16 and a drain region 17 are formed in the surface region of the substrate 11 with the floating gate 13 and the control gate 15 provided therebetween. An offset region 18 has a length 19. The above EPROM cell is disclosed in U.S. Pat. No. 4,814,286. The method of manufacturing the EPROM cell will be described below.
The length 19 of the offset region is defined by a photoresist 20 serving as a mask, as shown in FIG. 2. However, this method of defining the length 19 has the following drawbacks: first, it is difficult to form a fine offset region; and second, the length cannot be controlled satisfactorily, since it depends on the mask aligning process.
To overcome these drawbacks, the length of an offset region may be defined by a method as shown in FIG. 3. In this method, ions are injected into the substrate, thereby forming source and drain regions in the same manner as in the method shown in FIG. 2. An insulation film 22 made of, for example, an oxide film is formed by anisotropic etching on the side wall of the floating gate 13. Thereafter, ions are additionally injected into the substrate, using the insulation film 22 as a mask, thereby forming source and drain regions 16 and 17. As a result, a length 23 of an offset region is defined.
In this method, anisotropic etching is performed to form the insulating film 22. During the anisotropic etching, the upper surface of the floating gate 13 is exposed to the etching atmosphere and serves as an etching stopper layer. Hence, the upper surface of the floating gate 13 is damaged and becomes rough, and contaminants are easily deposited on the surface. As a result, the quality of the gate insulating film 14-1, which is formed between the floating gate 13 and the control gate 15, as shown in FIG. 1, is degraded. Accordingly, it is difficult to form a thin gate insulating film.
Moreover, in the above two methods, the gate oxide film, i.e. the insulation film 14-2 is formed on the offset region 18 by a thermal oxidation method. At the same time, the insulation film 14-1 is formed on the floating gate 13. Hence, it is difficult to set the thicknesses of the insulation films 14-1 and 14-2 to desirable values.
As described above, according to the conventional methods, the length of the offset region and the thickness of the gate insulation film are not satisfactorily controlled, and the quality of the gate insulation films is degraded.